Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes

Abstract

This paper describes the applicability of Tunnel FETs (TFET) to ultra-low-power sensor-node embedded Static Random-Access Memories (SRAM). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at Vdd=1V or lower. The Read and Write Static Noise Margins (SNM) are evaluated at 120mV and 200mV, with the operation speed of 3.8GHz and 800MHz Vdd=1V in read and write, respectively. The cell leakage is less than 5fA at Vdd=1V. A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 2 fW/cell or 48 pW for a 4 kB array.