Synthesis of Data-Parallel Algorithms for Programmable Logic Devices

Abstract

Behavioral high-level hardware design tools are currently considered powerful and can largely facilitate the hardware development cycle as a whole. Modern hardware design tools can target high-density programmable logic devices, such as, Field Programmable Gate Arrays. Currently, hardware/software co-design is witnessing a growing focus on finding alternative methods that could further improve the design process. In this paper, we explore the effectiveness and extend a formal methodology for hardware design. The method adopts a a step-wise refinement approach that starts development from formal specifications. A functional programming notation is used for specifying algorithms and for reasoning about them. The method is aided by off-the-shelf refinements based on the operators of Communicating Sequential Processes that map easily to programs written in Handel-C. Handel-C descriptions are directly compiled into reconfigurable hardware. The practical realization of this methodology is evidenced by a case studying data-parallel implementations of a matrix multiplication algorithm. The developed designs are compiled and tested under Agility's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of the presented implementations are included.