A new multi-channel on-chip-bus architecture for system-on-chips

Abstract

We can integrate more IP blocks on the same silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processor. However, most of existing SoC buses have bottleneck in on-chip communication because of a shared bus architecture, which results in the performance degradation of the system. In most cases, the performance of multi-processor systems is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of processors. We propose an efficient SoC network architecture (SNA) using crossbar router which provides a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels. According to the proposed architecture, we design components for the SNA and build a model system. The proposed architecture has a better efficiency by 40% than the AMBA AHB according to a simulation result.