Failure Mechanism of High Via Resistance Induced by Fluorine and Moisture

Abstract

High Via resistance for borderless Via design was detected at PCM E-test step during wafer fabrication. The high via resistance wafers were sent for TEM and EDX analysis to determine the failure root cause. From the TEM images, a layer of non-conductive material is seen at the Via hole bottom. EDX analysis and probe spectrum analysis confirmed the foreign material is Al-F-O compound. A Design of Experiment (DOE) was carried out to determine the dominant factor contributing to the formation of the Al-F-O material after post Via etch clean.