A 5.8GHz low-IF multi-data rate GFSK transceiver with clock recovery and integrated 21dBm power amplifier

Abstract

A highly integrated 5.8 GHz transceiver capable of supporting multiple data rates has been designed in 0.18 um SiGe BiCMOS for digital cordless phones and streaming audio applications. It also has a clock data recovery (CDR) circuit which can be supplied to baseband chips in conjunction with the digital received data. The transmitter with an integrated power amplifier consumes 185 mA achieving an output power of 20.5 dBm and the receiver consumes 65 mA achieving a sensitivity of -103.5 dBm and -101.5 dBm at 1.536 Mbps and 2.048 Mbps respectively. The active area is 7.3 mm2.