A recursive fast multiplier

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284) Pub Date : 1998-12-01 DOI:10.1109/ACSSC.1998.750853

A. Danysh, E. Swartzlander

引用次数: 34

Abstract

This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.

查看原文本刊更多论文

递归快速乘法器

提出了一种递归快速乘法算法。本文定义了该算法，并将其应用于2的补号乘法。给出了详细讨论体系结构和逻辑实现的逐步方法。一个随机、自检的仿真程序验证了递归乘法算法的正确性。本文分析了该设计的速度和门数，并将结果与其他乘法器设计进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)

自引率

0.00%

发文量