Layout-level techniques for testability improvement of MOS physical designs

Abstract

A methodology for physical testability assessment is reviewed, and a technique to enhance the physical testability of ICs with BIST (built-in self test) is presented. It is shown that an appropriate choice of a primitive polynomial can improve the realistic fault coverage, obtained with pseudorandom test patterns or, conversely, can lead to reduced test lengths, for the same fault coverage. The results are ascertained by the physical design and linear feedback shift register specification of a self-test ALU (arithmetic logic unit).<>