FPGA Implementation of High Speed 64-Bit Data Width True Random Number Generator using Clock Managers With Metastability

Abstract

Currently, cybersecurity plays a crucial role in various fields to ensure secure data communication. True Random Number Generators (TRNGs) are crucial components for many critical security applications. While analog-based entropy sources are often used in digital-based solutions, there is a high demand for digital-based solutions, especially for Field Programmable Gate Array (FPGA)-based digital systems. A unique technique has been developed to simplify the design of TRNGs on FPGA devices. This technique utilizes the runtime capabilities of the hardware primitives provided by the Digital Clock Manager (DCM) to adjust the phase shift between two clock signals. An auto-tuning approach automatically adjusts the phase difference between the clock signals to force one or more flip-flops (FFs) to enter the metastability zone, which is used as a source of unpredictability in the system. Additionally, the fast carry-chain hardware primitive is uniquely used to further enhance the randomness of the generated bits. Lastly, a powerful on-chip post-processing strategy is employed to prevent any interference with the TRNG output. This work was implemented in verilog HDL, with 32 and 64 data width, and synthesized in Xilinx Zynq FPGA. The characteristics of the TRNG design were evaluated based on area, delay, and power consumption.