Verticalization Of Direct Structural Table In Synthesis Of Mealy FSMS For FPGAs

A. Bukowiec, A. Barkalov
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引用次数: 2

Abstract

The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal possible number of bits. In this case only one decoder is used for implementation of the microoperations system. This method permits to minimize a number of outputs of the combinational part of Mealy FSM in comparison with the same characteristic of Mealy FSM with encoding of fields of compatible microoperations
fpga粉状FSMS合成中直接结构表的垂直化
提出了在实现有限状态机(FSM)虚输出逻辑电路的FPGA器件中减少逻辑量的方法。该方法基于直接结构表(DST)中微指令的垂直化。由于垂直化的结果,直接结构表的所有微操作都是兼容的。它允许用尽可能少的比特数对每个微操作进行编码。在这种情况下,只使用一个解码器来实现微操作系统。与具有兼容微操作域编码的面点FSM的相同特性相比,该方法可以使面点FSM的组合部分的输出数量最小化
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