Capacitance-voltage hysteresis of MIS device with PMMA:TiO2 nanocomposite as gate dielectric

Abstract

In this paper we study the hysteresis in metal-insulator-semiconductor (MIS) devices fabricated with nanocomposite poly (methyl methacrylate): titanium dioxide (PMMA:TiO2) on n-tyse Si as dielectric and semiconductor layers, respectively. The capacitance-voltage (C-V) and current-voltage (I-V) characteristic of MIS were studied as a function of different frequency varied at 10 kHz until 10 MHz. C-V measurement were carried out by applying the sweeping voltage form -8V to +6V. Meanwhile for I-V measurement the applied voltage is from -5V to +5V. From the C-V curve, it shows typical behavior of n-type MIS. As the frequency increased, the maximum capacitance, Cmax is reduced. Transition from accumulation to depletion region are faster at frequency 10MHz compare to 10 kHz is due to the reactions of mobile charge carriers at the interface dielectric-semiconductor layer. When we applied positive and negative voltage bias to the MIS there is shifting in flat band voltage, VFB. The shifting is towards negative direction (more negative voltage) that is due to the charge trapping in the dielectric-semiconductor interface. Similar characteristics were at I-V results which showing shifting to more negative voltage proven that electrons are temporarily trapped and de-trapped at the interface of dielectric-semiconductor layer.