J. Myers, J. Hejase, Junyan Tang, S. Chun, W. Becker, D. Dreps
{"title":"Signal Integrity Considerations of PCB Wiring in Tightly Pitched Module Pin Fields of High Speed Channels","authors":"J. Myers, J. Hejase, Junyan Tang, S. Chun, W. Becker, D. Dreps","doi":"10.1109/EPEPS47316.2019.193216","DOIUrl":null,"url":null,"abstract":"Effects of PCB wiring in tightly pitched module pin fields on high speed channel signal integrity are evaluated in this paper. Three different module orthogonal pin pitches are considered: 0.8mm, 1.06mm and 1.27mm. Each of the pin pitch scenarios is represented through corresponding PCB via and PCB pin area wiring models. Frequency domain SI metrics, at 16GHz, of a full end to end channel including the different tightly pitched module PCB wiring scenarios are quantified, compared and discussed. Additionally, full channel time domain eye simulations carried out at 32Gb/s are used to evaluate effects on eye opening and correlate with the frequency domain observations.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS47316.2019.193216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Effects of PCB wiring in tightly pitched module pin fields on high speed channel signal integrity are evaluated in this paper. Three different module orthogonal pin pitches are considered: 0.8mm, 1.06mm and 1.27mm. Each of the pin pitch scenarios is represented through corresponding PCB via and PCB pin area wiring models. Frequency domain SI metrics, at 16GHz, of a full end to end channel including the different tightly pitched module PCB wiring scenarios are quantified, compared and discussed. Additionally, full channel time domain eye simulations carried out at 32Gb/s are used to evaluate effects on eye opening and correlate with the frequency domain observations.