Application Of Tab In High Performance Single Chip Package

Y. Stricot, P. Couranti, G. Dehaine
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引用次数: 1

Abstract

The increase of the speed and of the number of I/O’s of integrated circuits requires High Performance Single Chip Packages. TAB packages offer an attractive alternative to the standard ceramic QFP in terms of electrical performances and cost reduction. In this paper, a new package using both ceramic and TAB construction is described. It has been designed for a large (12mm Sa) CMOS VLSI with 316 I/O’s. The 276 outer leads have a 0.32 mm pitch. The footprint on the board is 29.2 mm SQ. This work has been sponsorized by the European Community and developed during the Esprit project APACHI P . The package structure will be fully described. Its two major elements are a TAB frame using the two or three layers technology (one metal layer) and a plane capacitor mixing the polyimide and the cofired processes. So, the MLB (Mid lead bonding) connection is introduced: the power leads of the frame are connected to this plane capacitor as close as possible to the chip (0.3 mm). This connection allows a reduction of the noise appearing during the simultaneous switching of the buffers (up to 40 at SO mA/ns per buffer). Electrical modelisations have been conducted to define the equivalent network. We have selected specific organic adhesives to assemble the structure. To connect the lead on the chip (ILB) and the leads on the ceramic (MLB) single point bonding techniques have been applied. The reason is that in this application the chip on tape is placed in a non-hermetic environment, the encapsulation process is very important. By using flexible adhesives we have solved the attachment of the die directly on a brass piece to minimize the high mechanical stresses in the chip. For the lead-frame attachment, we use specific thin films adhesives(100 microns thick) to assemble kapton or upilex. After trim and form of the leads, hot bars reflow soldering is used to mount the package on the board. The characterization of the package has shown its excellent behavior in terms of reliability, of thermal resistance and of electrical performances for high speed applications.
标签在高性能单片机封装中的应用
集成电路的速度和I/O数量的增加需要高性能的单片机封装。TAB封装在电气性能和降低成本方面为标准陶瓷QFP提供了一个有吸引力的替代方案。本文介绍了一种采用陶瓷和TAB结构的新型封装。它是为具有316 I/O的大型(12mm Sa) CMOS VLSI设计的。276外部引线有0.32毫米的间距。电路板上的占地面积为29.2平方毫米。这项工作得到了欧洲共同体的赞助,并在Esprit项目APACHI P期间进行了开发。包结构将被完整地描述。它的两个主要元素是使用两层或三层技术(一层金属层)的TAB框架和混合聚酰亚胺和共烧工艺的平面电容器。因此,引入了MLB (Mid lead bonding)连接:框架的电源引线连接到尽可能靠近芯片的平面电容器(0.3 mm)。这种连接可以减少同时切换缓冲器期间出现的噪声(每个缓冲器在SO mA/ns时高达40)。已经进行了电气建模来定义等效网络。我们选择了特定的有机粘合剂来组装结构。为了连接芯片上的引线(ILB)和陶瓷上的引线(MLB),采用了单点键合技术。原因在于,在这种应用中,磁带上的芯片放置在非密封环境中,封装过程非常重要。通过使用柔性粘合剂,我们解决了模具直接附着在黄铜片上的问题,以尽量减少芯片中的高机械应力。对于引线-框架连接,我们使用特定的薄膜粘合剂(100微米厚)来组装卡普顿或upilex。在修剪和形成引线后,热棒回流焊接用于将封装安装在电路板上。封装的特性表明其在可靠性,热阻和高速应用的电气性能方面具有优异的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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