{"title":"Application Of Tab In High Performance Single Chip Package","authors":"Y. Stricot, P. Couranti, G. Dehaine","doi":"10.1109/IEMT.1992.639860","DOIUrl":null,"url":null,"abstract":"The increase of the speed and of the number of I/O’s of integrated circuits requires High Performance Single Chip Packages. TAB packages offer an attractive alternative to the standard ceramic QFP in terms of electrical performances and cost reduction. In this paper, a new package using both ceramic and TAB construction is described. It has been designed for a large (12mm Sa) CMOS VLSI with 316 I/O’s. The 276 outer leads have a 0.32 mm pitch. The footprint on the board is 29.2 mm SQ. This work has been sponsorized by the European Community and developed during the Esprit project APACHI P . The package structure will be fully described. Its two major elements are a TAB frame using the two or three layers technology (one metal layer) and a plane capacitor mixing the polyimide and the cofired processes. So, the MLB (Mid lead bonding) connection is introduced: the power leads of the frame are connected to this plane capacitor as close as possible to the chip (0.3 mm). This connection allows a reduction of the noise appearing during the simultaneous switching of the buffers (up to 40 at SO mA/ns per buffer). Electrical modelisations have been conducted to define the equivalent network. We have selected specific organic adhesives to assemble the structure. To connect the lead on the chip (ILB) and the leads on the ceramic (MLB) single point bonding techniques have been applied. The reason is that in this application the chip on tape is placed in a non-hermetic environment, the encapsulation process is very important. By using flexible adhesives we have solved the attachment of the die directly on a brass piece to minimize the high mechanical stresses in the chip. For the lead-frame attachment, we use specific thin films adhesives(100 microns thick) to assemble kapton or upilex. After trim and form of the leads, hot bars reflow soldering is used to mount the package on the board. The characterization of the package has shown its excellent behavior in terms of reliability, of thermal resistance and of electrical performances for high speed applications.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1992.639860","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The increase of the speed and of the number of I/O’s of integrated circuits requires High Performance Single Chip Packages. TAB packages offer an attractive alternative to the standard ceramic QFP in terms of electrical performances and cost reduction. In this paper, a new package using both ceramic and TAB construction is described. It has been designed for a large (12mm Sa) CMOS VLSI with 316 I/O’s. The 276 outer leads have a 0.32 mm pitch. The footprint on the board is 29.2 mm SQ. This work has been sponsorized by the European Community and developed during the Esprit project APACHI P . The package structure will be fully described. Its two major elements are a TAB frame using the two or three layers technology (one metal layer) and a plane capacitor mixing the polyimide and the cofired processes. So, the MLB (Mid lead bonding) connection is introduced: the power leads of the frame are connected to this plane capacitor as close as possible to the chip (0.3 mm). This connection allows a reduction of the noise appearing during the simultaneous switching of the buffers (up to 40 at SO mA/ns per buffer). Electrical modelisations have been conducted to define the equivalent network. We have selected specific organic adhesives to assemble the structure. To connect the lead on the chip (ILB) and the leads on the ceramic (MLB) single point bonding techniques have been applied. The reason is that in this application the chip on tape is placed in a non-hermetic environment, the encapsulation process is very important. By using flexible adhesives we have solved the attachment of the die directly on a brass piece to minimize the high mechanical stresses in the chip. For the lead-frame attachment, we use specific thin films adhesives(100 microns thick) to assemble kapton or upilex. After trim and form of the leads, hot bars reflow soldering is used to mount the package on the board. The characterization of the package has shown its excellent behavior in terms of reliability, of thermal resistance and of electrical performances for high speed applications.