New Concepts for Wordline Driving Circuits in CMOS Dynamic Random Access Memories

Abstract

NMOS-type circuits for wordline driving circuits in CMOS-DRAMs are discussed. Associated reliability risks and circuit design problems are shown. As a solution to these problems, a new concept using true CMOS circuitry for wordline driving circuits is presented. Simulation results indicate significant advantages. Measurement results obtained from a realization on a 4 Megabit DRAM are presented at the conference.