CBGA package design for C4 PowerPC microprocessor chips: trade-off between substrate routability and performance

Abstract

Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<>