FPGA-based Architectures to Recover from Hardware Trojan Horses, Single Event Upsets and Hard Failures

Abstract

Third-party IPs (3PIPs) may have a Hardware Trojan Horse (HTH) that escaped detection during the testing phase. This paper proposes two techniques to recover from a HTH during runtime. In the context of FPGA-based systems, it will be proven that these techniques can simultaneously recover from Single Event Upsets (SEUs), Hard Failures (HFs) as well as HTHs in permanent and temporary modules. The architectures can detect the type of fault and in some cases the identity of the 3PIP with the HTH. A DE10-Standard FPGA development board with Cyclone V devices was used to successfully test and simulate (using Modelsim) the proposed designs and compiled with Quartus v18.1.