{"title":"3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs","authors":"T. Holtij, M. Graef, A. Kloes, B. Iñíguez","doi":"10.1109/ESSDERC.2014.6948809","DOIUrl":null,"url":null,"abstract":"A 3-D analytical and physics-based compact model for extremely scaled junctionless (JL) triple-gate nanowire (TG-NW) MOSFETs is presented. Based on Poisson's equation and the conformal mapping technique, a compact solution for the electrostatics is derived in 3-D. A current expression is presented, which is continuous in all regions of device operation, and which takes into account the specific behavior of JL transistors. The model is compared versus measurement and simulated data of JL TG-NW MOSFETs, whereby the structural model parameters equal the values given by the fabricated devices. Important electrical parameters, such as threshold voltage VT, drain-induced barrier lowering (DIBL) and subthreshold slope S are worked out.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 44th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2014.6948809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A 3-D analytical and physics-based compact model for extremely scaled junctionless (JL) triple-gate nanowire (TG-NW) MOSFETs is presented. Based on Poisson's equation and the conformal mapping technique, a compact solution for the electrostatics is derived in 3-D. A current expression is presented, which is continuous in all regions of device operation, and which takes into account the specific behavior of JL transistors. The model is compared versus measurement and simulated data of JL TG-NW MOSFETs, whereby the structural model parameters equal the values given by the fabricated devices. Important electrical parameters, such as threshold voltage VT, drain-induced barrier lowering (DIBL) and subthreshold slope S are worked out.