Efficient fixed-point refinement of DSP dataflow systems

Abstract

With the current extensive deployment of digital communications, new standards are required every few years to regularly provide with new features. More throughput and better radio coverage w.r.t. former standards are examples of mandatory improvements. Generally, a new standard consists in modifying elements of the systems incrementally: add a receive antenna, use higher order modulation, etc. The design methodology is then crucial to ensure system quality while maintaining a short time for delivery. This paper proposes to use dataflow modelling for its ability to represent complex systems at a high level of abstraction. The dataflow representation inputs a 2-step incremental design method that aims at ensuring perfect compliance to quality requirements. The method consists first in sizing interfaces and then defining process accuracy to reach the desired quality. The studied use case is a High Speed Downlink Packet Access (HSPDA) receiver type 2 where the channel equalizer replaces the RAKE receiver on an existing system. We show that the fast prototyping can be done by focusing only on the key blocks to reduce time-to-design. The fixed-point refinement is studied thoroughly and we show the quality constrained of 2.31 dB is maintained all through the design steps. It ensures performance independence to run simulations in parallel and keep the time-to-design reasonable.