Technology independent yield-aware place & route strategy for printed electronics gate array circuits

2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT) Pub Date : 2016-10-01 DOI:10.1109/CAD-TFT.2016.7785047

M. Llamas, J. Carrabina, L. Terés

引用次数: 0

Abstract

We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.

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印刷电子门阵列电路的技术独立产率感知位置和路径策略

我们提出了一种基于喷墨可配置门阵列(IGA)设计风格和数字印刷个性化的数字有机/柔性/印刷电子(PE)电路的新布局和路由(P&R)策略。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)

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