New chip scale package with CTE matching to the board

Abstract

This paper outlines a few of the more promising chip scale package configurations and discusses where they stand with respect to some of the ideal requirements for a CSP. These criteria are: low cost, a good fit to the infrastructure, and excellent board level reliability. Measured against these criteria, none of these packages has emerged as a clear winner. This paper will address a new patent pending chip scale package concept which has low cost potential, uses conventional wire bonding and overmolding processes and has been predicted through mechanical modeling to have excellent board level reliability. Instead of using an elastomeric interposer which decouples the stress of the die from the board, the strategy is to minimize the solder joint stress by instead incorporating a copper interposer which has a matching CTE to that of the board. The die is directly attached to the copper interposer using a standard low stress die attach adhesive. The carrier is supplied in a rigid strip format which can be easily handled with the conventional industry infrastructure. This package is currently being assembled for both a cavity up configuration (peripheral wire bonding to the die) and a cavity down variety (central bonding to the die, ex. DRAM).