Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes

Matthias Hiller, Michael Weiner, Leandro Rodrigues Lima, Maximilian Birkner, G. Sigl
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引用次数: 54

Abstract

Secret key generation with Physical Unclonable Functions (PUFs) is an alternative to conventional secure key storage with non-volatile memory. In a PUF, secret bits are generated by evaluating the internal state of a physical source. Typically, error correction is applied in two stages to remove the instability in the measurement that is caused by environmental influences. We present a new syndrome coding scheme, called Differential Sequence Coding (DSC), for the first error correction stage. DSC applies a fixed reliability criterion and searches the PUF output sequence sequentially until a number of suitable PUF outputs is found. This permits to guarantee the reliability of the indexed PUF outputs. Our analysis demonstrates that DSC is information theoretically secure and highly efficient. To the best of our knowledge, we are the first to propose a convolutional code with Viterbi decoder as second stage error correction for PUFs. We adapt an existing bounding technique for the output bit error probability to our scenario to make reliability statements without the need of laborious simulations. Aiming for a low implementation overhead in hardware, a serialized low complexity FPGA implementation of DSC and the Viterbi decoder is used in this work. For a reference SRAM PUF scenario, PUF size is reduced by 20% and the helper data size decreases by over 40% compared to the best referenced FPGA implementations in each class with a minor increase in the number of slices.
利用差分序列编码和卷积编码突破固定PUF块限制
使用物理不可克隆函数(puf)生成密钥是使用非易失性存储器的传统安全密钥存储的替代方案。在PUF中,通过评估物理源的内部状态来生成秘密位。通常,误差校正分两个阶段应用,以消除由环境影响引起的测量中的不稳定性。我们提出了一种新的综合征编码方案,称为差分序列编码(DSC),用于第一个纠错阶段。DSC应用一个固定的可靠性标准,并按顺序搜索PUF输出序列,直到找到一些合适的PUF输出。这样可以保证索引PUF输出的可靠性。我们的分析表明,DSC在理论上是信息安全的和高效的。据我们所知,我们是第一个提出带有维特比解码器的卷积码作为puf的第二阶段纠错的人。我们将现有的输出误码概率边界技术应用于我们的场景,从而在不需要费力的模拟的情况下做出可靠性声明。为了降低硬件的实现开销,本文采用串行化的低复杂度FPGA实现DSC和Viterbi解码器。对于参考SRAM PUF场景,与每个类中最佳参考FPGA实现相比,PUF大小减少了20%,helper数据大小减少了40%以上,切片数量略有增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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