Hiroki Matsutani, M. Koibuchi, Hiroshi Nakamura, H. Amano
{"title":"Run-Time Power-Gating Techniques for Low-Power On-Chip Networks","authors":"Hiroki Matsutani, M. Koibuchi, Hiroshi Nakamura, H. Amano","doi":"10.1007/978-1-4419-6911-8_2","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":299942,"journal":{"name":"Low Power Networks-on-Chip","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Low Power Networks-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-1-4419-6911-8_2","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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