Integrating Machine-Learning Probes into the VTR FPGA Design Flow

Abstract

This paper proposes a set of Machine-Learning (ML) probes that can be used at the placement step within the Verilog-to-Routing (VTR) tool. The proposed probes can pro-vide real-time feedback to the VTR placer guiding it towards more “router-friendly” placement solutions that result in the router performing fewer computationally expensive rip-up and re-route operations. In addition to enabling the previous strategies for reducing routing runtimes, the proposed probes can also be used to speed up architecture exploration by providing estimates of interconnect resource utilization on the Field Programmable Gate Array (FPGA) without incurring the computational cost of actually performing routing. Re-sults obtained indicate that the proposed ML probes not only improve upon all the VTR estimates in terms of wirelength, critical path delay and segmented wire utilization but also reduce the routing time of the tool.