Characteristics of gate inside junctionless transistor with channel length and doping concentration

Abstract

A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.