Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects

Abstract

Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.