Jie Lou, Christian Lanius, Florian Freye, Tim Stadtmann, T. Gemmeke
{"title":"All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy Efficiency","authors":"Jie Lou, Christian Lanius, Florian Freye, Tim Stadtmann, T. Gemmeke","doi":"10.1109/ESSCIRC55480.2022.9911382","DOIUrl":null,"url":null,"abstract":"This paper presents an all-digital time-domain compute-in-memory (TDCIM) engine for binary neural networks (BNNs), which is based on commercial standard cells facilitating technology mapping. The proposed TDCIM engine exploits energy-efficient computing principles, supports data reuse and employs double-edge triggered operation. Time domain wave-pipelining technique is also introduced to improve throughput by 1.5x while preserving accuracy. We use Structured Data-Path (SDP) placement and custom routing flow during place and route (P&R) to reduce systematic variations. The measured arrival time of different MAC results is sufficiently bounded to preserve accuracy across PVT variations. Fabricated in a 22nm process, the proposed BNN engine can achieve an energy efficiency of 1.05 POPS/W at 0.5V matching the accuracy of the PyTorch baseline of 99.14% on the MNIST dataset.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911382","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents an all-digital time-domain compute-in-memory (TDCIM) engine for binary neural networks (BNNs), which is based on commercial standard cells facilitating technology mapping. The proposed TDCIM engine exploits energy-efficient computing principles, supports data reuse and employs double-edge triggered operation. Time domain wave-pipelining technique is also introduced to improve throughput by 1.5x while preserving accuracy. We use Structured Data-Path (SDP) placement and custom routing flow during place and route (P&R) to reduce systematic variations. The measured arrival time of different MAC results is sufficiently bounded to preserve accuracy across PVT variations. Fabricated in a 22nm process, the proposed BNN engine can achieve an energy efficiency of 1.05 POPS/W at 0.5V matching the accuracy of the PyTorch baseline of 99.14% on the MNIST dataset.