Minimization of the High-Level Fault Model for Microprocessor Control Parts

Abstract

The paper presents a method for representing the instruction set truth tables of microprocessors with High-Level Decision Diagrams (HLDD). A behavior level fault model is defined for the microprocessor control parts on the basis of instruction level truth tables (TT). Two methods are proposed for creating HLDDs from TTs with minimization of the edges on graphs: greedy algorithm, and branch and bound algorithm (B&B). A simple and fast computable lower bound is proposed to be used for pruning the search space of the B&B algorithm. Experimental data of using the fault model for several microprocessors and comparison data are provided to show the efficiency of the proposed high-level fault model over the gate-level Stuck-at-Fault (SAF) model.