VLSI concurrent error correcting adders and multipliers

Abstract

Time redundancy is an approach to achieve fault-tolerance without introducing excessive hardware that can be used in applications where time is not critical. The basic recomputing with duplication with comparison error-detecting adder propsed by Johnson was extended to perform error correction in both adders and multipliers. VLSI designs of time redundant error-detecting and error-correcting adders and multipliers are shown. Their hardware overhead is much lower than that of hardware redundancy approaches and the delay penalty is reasonable. Hence they are useful in systems where hardware complexity is the primary concern.