Towards an Improved Implementation of Hardware Transactional Memory on Asymmetric Processors

Abstract

The paper describes typical challenges in a computer architecture research demonstrated on a case study of hardware transactional memory. It shows how the proposed concepts and solutions are implemented in a software simulator. Then, various experiments are carefully prepared in order to evaluate the performance of the proposed transactional memory implementation. The transactional memory in our experiments was paired with an asymmetric multicore processor with a support for transaction migration. We present design decisions how to implement the transactional memory, the transaction migration and the different cache memory subsystem organization in the simulator. Also, we varied cache memory subsystem organization and parameters in the experiments. Important issue was also how to organize data collected from the experiments, and how to analyze and visually present them. Finally, the paper demonstrates the use of a benchmark suite for the transactional memory. Problems that we encountered during research are pointed out and discussed and solutions for them are provided. The paper concludes with brief lessons we have learned in this research effort.