Automatic peak detection system power analysis using system on a programmable chip (SoPC) methodology

Abstract

In this paper, a power analysis of a Nios II processor system is carried out. The methodology of power analysis includes SoPC (System on a Programmable Chip) system integration, architecture design compilation, software program compilation using a toolchain, system simulation and power analysis. In this work, a peak detection algorithm is implemented into the embedded processor system for power analysis. Several toggle rate settings are applied to the power analysis on the system architecture using the PowerPlay Power Analyser. Based on the power dissipation report, the estimated total power consumption is between 198.86 mW to 258.15 mW, while the core static power consumption is from 154.97 mW to 155.17 mW. The results show that performing power analysis with a higher number of signal activities means it is possible to increase the accuracy of the estimated power consumption.