{"title":"An Active Double-Balanced Down-Conversion Mixer in InP/Si BICMOS Operating from 70-110 GHz","authors":"J. Mccue, M. Casto, J. Li, P. Watson, W. Khalil","doi":"10.1109/CSICS.2014.6978540","DOIUrl":null,"url":null,"abstract":"In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 μm InP HBTs are used in the signal path while the 90 nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip Marchand baluns feeding both the LO and RF ports. An IF buffer follows the mixer to improve matching and signal quality for testing. After de-embedding the balun and IF buffer, the mixer core achieves a peak conversion gain of 13 dB, a minimum DSB NF of 10 dB, and an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V supply.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2014.6978540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 μm InP HBTs are used in the signal path while the 90 nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip Marchand baluns feeding both the LO and RF ports. An IF buffer follows the mixer to improve matching and signal quality for testing. After de-embedding the balun and IF buffer, the mixer core achieves a peak conversion gain of 13 dB, a minimum DSB NF of 10 dB, and an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V supply.