FaSTAP/spl trade/ : A scalable anti-jam architecture for GPS

Abstract

This paper describes FaSTAP/spl trade/, a scalable architecture for suppression of GPS interference. FaSTAP is a novel, reduced complexity implementation of fully-adaptive space-time adaptive processing (STAP). The architecture is well-suited to low-power operation with most of the processing in a single ASIC or FPGA. A variety of methods for adaptive weight computation can be supported, including sample matrix inversion (SMI). A four-channel ASIC has been created that performs STAP beamforming or nulling with up to seven time taps. The design is scalable to other systems with parameter changes in VHDL (3 and 7 channel FPGAs have been produced). The design supports between one and seven STAP time taps, which is selectable by software, but larger tap lengths can be accommodated with minor changes. Test results are provided that demonstrate the performance against a variety of wideband and narrowband jamming types. Additional simulations are shown that demonstrate the performance improvement in multipath of FaSTAP compared with space-frequency adaptive processing (SFAP).