Exploring multiple levels of parallelism using BOPS' DSP

Proceedings. IEEE International Multi Topic Conference, 2001. IEEE INMIC 2001. Technology for the 21st Century. Pub Date : 2001-12-28 DOI:10.1109/INMIC.2001.995334

W. Latif, A. Shahid, F. Saud, S. Ali, S.A. Khan

引用次数: 0

Abstract

A study of high performance, reusable and scalable DSP architecture of BOPS, which targets specific applications, is carried out. The degree of parallelism supported by the BOPS' ManArray architecture and its usability is tested on various algorithmic building blocks along with the more complex and irregular algorithm of the G.729a vocoder, a key requirement of VoIP gateway DSP engine. An analysis to reduce complexity as well as implementation of G.729a on an array processor using various optimization techniques is presented.

查看原文本刊更多论文

使用BOPS的DSP探索多层并行性

针对BOPS的具体应用，研究了高性能、可重用、可扩展的DSP体系结构。BOPS的ManArray架构支持的并行度及其可用性在各种算法构建块以及更复杂和不规则的G.729a声码器(VoIP网关DSP引擎的关键要求)上进行了测试。本文分析了利用各种优化技术降低G.729a在阵列处理器上的复杂度和实现方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings. IEEE International Multi Topic Conference, 2001. IEEE INMIC 2001. Technology for the 21st Century.

自引率

0.00%

发文量