Design and Implementation of an Efficient Dadda Multiplier Using Novel Compressors and Fast Adder

Abstract

Fast multipliers play a significant role in digital signal processing (DSP) and Arithmetic Logic Unit (ALU) systems. Delay and area are cardinal factors that limit the performance of a VLSI design circuit. The paper focuses on new approaches to Dadda Multiplier using Novel compressor designs. Two novel 4-2 compressors and modified higher order compressors are introduced. Three multiplier designs are proposed and compared with existing multiplier designs. Proposed design is found to be more optimal with the existing design in terms of delay and area, and can be used for exact multiplier applications. The designs are simulated using Xilinx ISE tool.