Innovative practices session 9C DFT and data for diagnostics

Abstract

Diagnosis driven yield analysis (DDYA) based on layout aware diagnosis results for volume failure data has been widely adopted for yield learning. Layout aware diagnosis analyzes failure test data and calls out suspects of interconnect bridges and interconnect opens, and cells at cell boundary. Recently the semiconductor industry is seeing an increasing number of cell internal defects for FinFET technology, due to extremely small feature size, complex cell design and sophisticated manufacturing process. Cell aware diagnosis (CAD) has been proposed to pinpoint the defect location within a defective cell by using accurate defect models derived from analog simulation. Based on CAD results with accurate cell internal defect information, DDYA flow can handle cell related yield limiters better and thus speed up the yield ramp for FinFET technology.