Design of fault-tolerant solid state mass memory

Abstract

This paper presents the flow used for the design of a fault-tolerant solid state mass memory (SSMM) based on commercial off the shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiations on these devices are often complex. In particular, in the paper we consider heavy ion and proton induced soft and hard errors in DRAM devices. In our work, these errors are mitigated at system level rather at device level. In fact the mass memory is based on a suitable ECC code that improves its tolerance with respect to errors induced in DRAMs. The definition of a SSMM architecture is very complex since the design has to take into account the radiation environment and the different system constraints. In this paper we presents the methodology, derived from the operational research theory, used to select the codes and the memory architecture, taking into account the different design constraints.