400-Watt Doherty amplifier linearization using optimized memory polynomials predistorter

Abstract

This paper deals with the optimization of the memory polynomial predistorter complexity when used to compensate the nonlinear behavior of Power Amplifier (PA) exhibiting strong memory effects. The effectiveness of memory polynomials is validated experimentally using a realistic 400-Watt Doherty high power base station amplifier lineup. The performance of the Digital Predistortion (DPD) was evaluated using realistic test signals: one, and four carrier WCDMA. The use of DPD to compensate for the distortion in Doherty Power Amplifier yielded significant increases in performance: a 100% increase in Power Added Efficiency (PAE). In addition the complexity of the memory polynomial DPD was reduced by over half, as direct results of the reduction of the number of coefficients, while maintaining good performance.