FAST SIGNATURE COMPUTATION FOR LINEAR COMPACTORS

Abstract

Compaction simulation time is a costly (CPU) process when performing fault simulation of BIST circuits. In this paper, we present a compaction simulation algorithm for linear compactors. Basic look-up operations are used to reduce compaction time significantly and memory requirements for the tables are small. With this algorithm, the compaction of an M-bit sequence by a k-bit linear compactor requires M + s2 7 k-bit words of memory where s, 1 and m can be any value such that T and f are integers, and where pAerr is the proportion of errors in the signature and pRSrr the proportion of errors in the CUT’S response. Both pRSTr and pAeTr range between [0,1]. However, for a large proportion of faults in a CUT, the detection probabilities are low, making pAS7? and pR,?? low as well. Simulation results demonstrating the speed of the compaction algorithm are given. + s pR.,, ) + operations and 12 x(‘ P A s r t