Deadlock detection and avoidance using Signal Interpreted Petri Nets

Abstract

Ladder Logic Diagram (LLD) modeling is a popular method that is used in designing programmable logic controllers (PLC) for industrial automation. However, as systems get more complex, they become increasingly difficult to detect and debug for design problems using these LLD models. Deadlock is one of the critical problems faced in complex PLCs applied in industry today. This paper proposes a method to analyse the deadlock problem in an LLD model. The LLD model is first converted to an equivalent Signal Interpreted Petri Net (SIPN). Deadlocks are detected by applying the approach of transitive matrix of resource share places in this SIPN. A new deadlock avoidance algorithm is proposed, that uses the Boolean transitions of the SIPN model. A key advantage of the proposed algorithm over existing methods is that there are no additional elements or resources introduced to eliminate the deadlock problem. Thus, the complexity of the net remains unchanged.