Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint

Abstract

Floorplanning is one of the most important steps in the physical design. Traditional floorplanning focuses on minimizing wirelength and area. As design complexity grows, more and more nets need to be routed in a chip, which makes routing difficulty increase dramatically in modern ICs. Hence, it is necessary to consider net routability during floorplanning. This paper proposes the first work to consider routability and wirelength in floorplanning with fixed-outline constraint by using an analytical based approach. To estimate congestion more accurately, we also propose a new model to measure net usages, and transform the model into differentiable functions such that they can be solved by the optimization approach. The proposed method is efficient and effective, and the experimental results demonstrate the approach can actually reduce overflows without increasing routing wirelength.