Design of novel Vedic asynchronous digital signal processor core

Abstract

In this era of rapidly growing technology, Digital Signal Processing (DSP) is one of the core technologies having applications in various fields. This paper discusses about the design of an 8 bit fixed point, asynchronous Vedic DSP processor core. This novel architecture exploits the principles of asynchronous design using micro-pipelining methodology and also Vedic mathematics. Asynchronous design style eliminates clocking issues and reduces about 40% of the total power consumption [12]. An efficient Vedic multiplier proposed in this paper utilizes the following sutras: Urdhva - tiryagbhyam, Nikhilam Navatashcaramam Dastaha, Ekadhikena Purvena, Ekanyunena Purvena, Anurupyena, Antyayor Dasakepi. A novel Vedic divider is also presented using the following sutras: Nikhilam, Paravartya Yojayet, Urdhva Tiryakbhyam and Dhvijanka. This paper deals the novel architecture and design of low power Vedic DSP core using asynchronous logic style.