Modeling of power supply parasitics for selecting on-wafer bypass capacitance in high-speed IC designs

Abstract

We have developed a model for power supply parasitics to select properly the on-wafer bypass capacitor values in high-speed IC designs. The model can allows the chip area to be minimized while maintaining circuit performance. The procedures to develop this model are described and are suitable for all device technologies. An InGaP/GaAs HBT transimpedance amplifier with 10-GHz bandwidth was designed and fabricated. The simulation with the model matches the measured results very well.