Performance Analysis of Fixed Point FIR Filter Architectures

Abstract

In digital signal processing and communication systems, FIR filters have important role. One of the main challenges in Very Large Scale Integration(VLSI) signal processing is the FIR filter structure with optimized parameters. These filters made up of many adders and multipliers. In FIR filter, multiplier consumes high amount of power. The most important three areas in VLSI are power, area, and delay. This paper compares different types of fixed point FIR filter architectures and analyze the different perfomance parameters such as area, hardware utlization and delay. Different FIR filter architectures such as the conventional method, systolic architecture, associativity transformation and combination of systolic and associativity transformation architectures are considerd. We implemened a 4, 8 and 16 tap filters using the above mentioned architecures and compared their perfomance characteristics.