A reconfigurable low-power high-performance matrix multiplier architecture with borrow parallel counters

Abstract

A novel run-time reconfigurable matrix processor and its prototype implementation with new circuits, called borrow parallel counters, achieving low power, high speed, simple inter-connections and extra compact design, are presented. For typical graphics and image applications, the multiplier can produce in parallel the products of four 4/spl times/4 matrix pairs of 8-bit data, or two matrices X(4/spl times/4) and Y(4/spl times/4) of 16-bit data, or two matrices X(4/spl times/4) and Y(4/spl times/4) of 32-bit data, or two 64-b numbers. The proposed parallel counters utilize 4-bit 1-hot integer encoding and borrow bits, i.e. input bits of weight 2, effectively merging type-conversions and additions through using a unique embedded full adder circuit.