C. Wicpalek, T. Mayer, L. Maurer, U. Vollenbruch, Y. Liu, A. Springer
{"title":"Analysis and Measurement of Spurious Emission and Phase Noise Performance of an RF All-Digital Phase Locked Loop using a Frequency Discriminator","authors":"C. Wicpalek, T. Mayer, L. Maurer, U. Vollenbruch, Y. Liu, A. Springer","doi":"10.1109/MWSYM.2007.380398","DOIUrl":null,"url":null,"abstract":"A frequency discriminator in all-digital phase locked loops (ADPLLs) for RF-synthesis has to fulfill several tough requirements. The most important requirements are the in-band phase noise performance and knowledge about offset frequencies of the spurious emissions, because the ADPLL should fulfill several wireless communication standard requirements like UMTS and GSM. This paper presents a theoretical derivation, simulative analysis, and measurement results for the in-band phase noise level and the offset frequencies of spurious emissions of an ADPLL with a two-bit Frequency Discriminator implemented in a standard 0.13 mum CMOS technology","PeriodicalId":213749,"journal":{"name":"2007 IEEE/MTT-S International Microwave Symposium","volume":"58 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE/MTT-S International Microwave Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2007.380398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A frequency discriminator in all-digital phase locked loops (ADPLLs) for RF-synthesis has to fulfill several tough requirements. The most important requirements are the in-band phase noise performance and knowledge about offset frequencies of the spurious emissions, because the ADPLL should fulfill several wireless communication standard requirements like UMTS and GSM. This paper presents a theoretical derivation, simulative analysis, and measurement results for the in-band phase noise level and the offset frequencies of spurious emissions of an ADPLL with a two-bit Frequency Discriminator implemented in a standard 0.13 mum CMOS technology
用于射频合成的全数字锁相环(adpll)中的鉴频器必须满足几个苛刻的要求。最重要的要求是带内相位噪声性能和对杂散发射偏移频率的了解,因为ADPLL应该满足UMTS和GSM等几种无线通信标准的要求。本文提出了一个理论推导,模拟分析,并测量结果带内相位噪声水平和杂散发射的偏移频率的ADPLL与一个标准的0.13 μ m CMOS技术实现的2位鉴频器