Mutation-based validation of high-level microprocessor implementations

Abstract

In this paper we present a preliminary method of validating a high-level microprocessor implementation by generating a test sequence for a collection of abstract design error models that can be used to compare the responses of the implementation against the specification. We first introduce a general description of the abstract mutation-based design error models that can be tailored to span any coverage measure for microprocessor validation. Then we present the clustering-and-partitioning technique that single-handedly makes the concurrent design error simulation of a large set of design errors efficient and allows for the acquisition of statistical data on the distribution of design errors across the design space. We finally present a method of effectively using this statistical information to guide the ATPG efforts.