Redundancy in number representations as an aspect of computational complexity of arithmetic functions

Abstract

Introduction Recent research has led to the derivation of bounds for the time required to perform arithmetic operations by means of logical elements with a limited number of inputs [1]–[4]. The model of a (d, r) logical circuit C employed in these studies consists of a set of (d, r) logical elements and a rule of interconnection with designated sets of input and output lines. The (d, r) logical element has r input lines and one output line; these lines can assume one of d distinct states. The (d, r) logical element has a unit time delay; that is, the state of the output line at the time t+1 is a function of the states of the input lines at time t.