Low-Loss Low-Cost All-Silicon CMOS NLTLs for Pulse Compression

Abstract

This paper discusses the design of all-silicon pulse-compression nonlinear transmission lines (NLTLs), using a standard 0.18-mum CMOS process. Two different types of varactors based on NMOS transistors are investigated. One type is used in a single-edge, the other in a double-edge pulse-sharpener NLTL. To reduce the loss caused by conductive silicon substrate, a slow-wave transmission line technique is used. A measured S21 loss of only 0.25 dB/mm at 40 GHz is achieved. Both NMOS varactor and slow-wave coplanar-waveguide (CPW) transmission-line components for use in NLTL designs were fabricated and on-chip measurements were made. Transient simulations based on the measurements show a leading edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening.