1.7-W 50-Gbit/s InP HEMT 4:1 multiplexer IC with a multi-phase clock architecture

Abstract

Low-power and high-speed operation of a 4:1 multiplexer IC with a multi-phase clock architecture is reported. The architecture features a toggle-type flip-flop (TFF) that generates a four-phase clock, and a series-gated 4:1 selector (SEL). The fabricated IC using InP HEMTs operates at 50 Gbit/s error-free with 1.71-W power consumption and 1-Vpp output amplitude. The power consumption is less than 1/3 that of a conventional tree-type InP HEMT 4:1 multiplexer IC and is achieved without any reduction of operation speed and output amplitude.