Backside silicon-embedded inductor using magnetic layer for shielding and inductance enhancement

Abstract

In this paper, a backside silicon-embedded inductor (BSEI) using a magnetic layer is proposed and studied for magnetic flux shielding and inductance enhancement. With the magnetic layer, the magnetic flux that goes under the BSEI chip is reduced by 2 to 3 times, and consequently the significant BSEI performance degradation in presence of a Cu die pad is effectively suppressed. The inductance of the BSEI is also enhanced by 30% with the magnetic layer. This makes the BSEI more promising for power supply-on-chip applications.