Advanced memory issues - Session 16

Abstract

Advancements in technology often bring an increasing array of challenges in memory design. Requirements for memory continue to drive designs toward higher densities, lower voltage, reduced power, and improved speed, while a high level of reliability must be maintained. This session presents solutions to many of the issues fought today in the development of advanced memories. Invited Paper 16-1, by the well known Dr. Kiyoo Itoh, opens the session with a presentation on the trends and challenges associated with low-voltage embedded RAMS. State-of-the-art low-voltage eDRAMs and eSRAMs are discussed as well as future prospects. Paper 16-2 addresses the challenge in embedded SRAMs of detecting cells with poor signal margin by introducing a test mode that allows variable sense-amp timing. Paper 16-3 presents design solutions required to build a short latency embedded 512kB L2 Cache that achieves 1.4GHz and 2.6W at 1.3V, 85C. Paper 16-4 discusses how process variation influences the failure mechanisms of SRAM cells and proposes a process tolerant Cache architecture. Paper 16-5 addresses neutron-induced errors in SRAM cells with an analysis of charge-collection-failure (CCF) mode as well as a new parasitic-bipolar-failure (PBF) mode. Design techniques for reduced soft error rate are proposed.